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VLSI Projects

ID TITLE OUTPUT
IEEE-VL0101 Low-Cost Sorting Network Circuits Using Unary Processing
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IEEE-VL0102 Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification
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IEEE-VL0103 Taming Spatiotemporal Chaos in Forced Memristive Array
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IEEE-VL0104 Bandwidth Enhancement to Continuous-Time Input Pipeline ADCs
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IEEE-VL0105 A DfT Insertion Methodology to Scannable Q-Flop Elements
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IEEE-VL0106 A Dual-Data Line Read Scheme for High-Speed Low-Energy Resistive Nonvolatile Memories
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IEEE-VL0107 Single-Chip Design for Intelligent Surveillance System
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IEEE-VL0108 High-Density SOT-MRAM Based on Shared Bitline Structure
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IEEE-VL0109 A Changing-Reference Parasitic-Matching Sensing Circuit for 3-D Vertical RRAM
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IEEE-VL0110 Design and Analysis of Energy-Efficient and Reliable 3-D ReRAM Cross-Point Array System
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IEEE-VL0111 Stateful Memristor-Based Search Architecture
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IEEE-VL0112 Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test
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IEEE-VL0113 DCMCS: Highly Robust Low-Power Differential Current-Mode Clocking and Synthesis
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IEEE-VL0114 Viewer-Aware Intelligent Efficient Mobile Video Embedded Memory
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IEEE-VL0115 Scalable Symbolic Simulation Based Automatic Correction of Modern Processors
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IEEE-VL0116 Configurable Logic Operations Using Hybrid CRS-CMOS Cells
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IEEE-VL0117 Thermal Management of Batteries Using Super capacitor Hybrid Architecture With Idle Period Insertion Strategy
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IEEE-VL0118 Three-Dimensional Pipeline ADC Utilizing TSV/Design Optimization and Memristor Ratioed Logic
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IEEE-VL0119 Energy- and Area-Efficient Spin–Orbit Torque Nonvolatile Flip-Flop for Power Gating Architecture
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IEEE-VL0120 Cascade and LC Ladder-Based Filter Realizations Using Synchronous Time- Mode Signal Processing
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IEEE-VL0121 Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits
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IEEE-VL0122 Zero-Power Feed-Forward Spur Cancelation for Supply Regulated CMOS Ring PLLs
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IEEE-VL0123 Systematic Design of an Approximate Adder The Optimized Lower Part Constant- ORAdder
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IEEE-VL0124 A Framework for Enabling Fast Voltage Over scaling Simulation for Approximate Computing Circuits
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IEEE-VL0125 Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add
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IEEE-VL0126 On Synthesizing Memristor Base Logic Circuits With Minimal Operational Pulses
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IEEE-VL0127 Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks
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IEEE-VL0128 Duty-Cycle-Based Controlled Physical Unclonable Function
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IEEE-VL0129 Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications
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IEEE-VL0130 Toward an Energy Efficient High-Voltage Compliant Visual Intracortical Multichannel Stimulator
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IEEE-VL0131 Design Considerations for Energy-Efficient and Variation-Tolerant Nonvolatile Logic
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IEEE-VL0132 Stream Processing Dual-Track CGRA for Object Inference
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IEEE-VL0133 Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences
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